Samsung to More Than Double HBM4 Production Next Year

Samsung ramps up HBM4 output

Samsung announced it will more than double its production of HBM4 and HBM4E high‑bandwidth memory chips next year. The boost comes from expanding wafer capacity at its Pyeongtaek fab and adding a new line dedicated to the newest HBM stack.

The source, Sedaily, reports the plan targets a “more than double” increase, though it does not disclose exact volume figures. Samsung has not released a formal press statement, but industry insiders confirm the expansion will start in Q1 2027. The company already ships HBM3E at scale, and the new capacity will feed a growing queue of AI accelerator makers.

Why the surge matters now

AI training clusters consume terabytes of memory per node, and HBM remains the only memory that can keep up with GPU bandwidth. With Nvidia’s Hopper and AMD’s MI300X already demanding HBM4, a tighter supply could throttle next‑gen model training.

Competitors such as SK Hynix and Micron have announced HBM4 roadmaps, but neither has signaled a comparable scale‑up. Hynix hinted at a modest 30‑40% increase in HBM4 fab output for 2027, while Micron is still piloting its first HBM4 wafers. Samsung’s aggressive scaling therefore positions it as the likely default supplier for large‑scale AI cloud providers.

The move also reflects a broader shift in the memory market. DRAM volumes have plateaued as data‑center workloads migrate to specialized memory. High‑bandwidth stacks now command premium pricing, and the supply‑demand gap has pushed spot prices up 15% year‑over‑year, according to market tracker DRAMeXchange.

Technical challenges of doubling HBM4/E

HBM4 stacks use a 1‑nanometer class process for the logic layer and a 2‑nanometer class process for the DRAM die. Packing 16‑32 GB per stack while maintaining signal integrity pushes the limits of TSV (through‑silicon via) density. Doubling output means Samsung must replicate a highly complex integration flow without sacrificing yield.

The company has reportedly introduced a new wafer‑level test station that can validate TSV continuity in under five minutes, cutting the test bottleneck that slowed HBM3 production. Additionally, Samsung is leveraging its 3‑D integration expertise from its HBM3E line to improve thermal management in the denser HBM4E variant, which adds an extra 10% bandwidth per pin.

Even with these advances, yield loss remains a risk. HBM stacks historically see yields around 70% for first‑generation products; incremental process refinements are required to push yields above 80% before the economics of a double‑up scale become viable. Samsung’s internal reports, cited by the Sedaily article, suggest yield improvements of 5‑7 percentage points from the new test station, but the numbers are still provisional.

What to watch next

The next data point to track is Samsung’s first full‑year shipment numbers for HBM4/E, expected in the Q2‑Q3 2027 earnings call. Analysts will compare those figures against the projected demand from Nvidia’s upcoming Hopper‑X and AMD’s next‑gen CDNA GPUs. A shortfall would likely trigger price spikes and could accelerate alternative memory strategies, such as Intel’s Foveros‑based stacked DRAM.

Equally important is the response from SK Hynix and Micron. If they announce comparable capacity expansions, the market may avoid a supply crunch. If not, Samsung could capture a dominant share of the high‑bandwidth memory market for the next three years, giving it leverage over pricing and design partnerships with the biggest AI cloud players.

Finally, watch the regulatory filings for Samsung’s Pyeongtaek expansion. Environmental impact assessments and local government approvals could delay the rollout, turning a strategic advantage into a logistical headache. The interplay between production capacity, yield improvements, and market demand will define the high‑bandwidth memory landscape well into the next decade.